From one source, Confluence generates:

• Verilog and VHDL netlists (synthesis, simulation)
• Cycle accurate C models (software, simulation)
• NuSMV models (formal verification)
• XML netlists (custom back-end tooling)
• Executable Models (open verification)

The Confluence compiler returns executable models providing bit and cycle accuracy with high simulation performance. The executable simulation models are controlled by a simple command and query language, making it easy to connect Confluence to any verification environment or programming language (SystemC, Java, Python, OCaml, etc.). Because the simulation kernels run optimized native code, even a Perl test-bench will yield performance on par with compiled HDL simulation.

Update
This release includes the initial FNF C model generator that enables a compilation path from Confluence to C. New features include a new simulator data structure, which enables running multiple simulation models at once, and provides access to all hierarchical named signals in a design. This release also includes the Icarus Verilog FNF generator, providing a path from Verilog to C, VHDL, NuSMV, and JHDL.