A full Verilog implementation of the 10/100 MBps Ethernet MAC level. It consists
of a synthesizable RTL core that provides all the features necessary to implement the Layer 2 protocol of the Ethernet standard. It is designed to run
according to the IEEE 802.3 and 802.3u specications that define the 10 and 100 Mbps Ethernet standards respectively. The implementation also includes a
Wishbone DMA interface.
The MAC is the portion of ethernet core that handles the CSMA/CD protocol for transmission and reception of frames. It peforms Frame Data Encapsulation and Decapsulation, Frame Transmission, and Frame Reception.
The complete system has been successfully tested on a Virtex 1600E.