The LEON core is a SPARC compatible integer unit developed for future space missions. It has been implemented as a
highly configurable, synthesisable VHDL model. To promote the SPARC standard and enable development of
system-on-a-chip (SOC) devices using SPARC cores, the European Space Agency is making the full source code freely
available under the GNU LGPL license.
The LEON-1 processor should be seen as a demonstrator of the LEON core. As such, it implements a minimum of
interfaces and functions. Once the LEON core has been fully verified, a more complete processor (LEON-2) will be
developed with functions such as PCI interface, floating-point unit and DRAM controller. |
The VHDL model is fully synthesisable and contains synthesis scripts for Synopsys-DC and Synplify. Targeting a 0.35 um
CMOS process (gate-array or std-cell), approximately 100 MHz can be reached with a gate count of 35 Kgates. The
processor also fits in an Altera 10K200E FPGA, utilising 65% of the device and running at 15 MHz or a Xilinx XCV300 at 45MHz.
- Set-associative caches with random, LRR or LRU replacement
- Cache-line locking
- Pipelining option on 16x16 integer multiplier
- Atmel ATC18 (0.18 um) port
- Virtex2 port
- Support for on-chip ram