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openEMS 0.31 Category: tool
Jean-Pierre Boniface 9 November 2013; 03:38
Open EMS is a free and open electromagnetic field solver using the FDTD method, work with Matlab or gnu Octave.
  License: GPL homepage download

DVKit 1.1.0 Category: tool
Matthew Ballance 28 September 2013; 22:39
DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, and shell code

Add support for editing PERL and Python files. Update included packages.

  License: Other homepage download

asco 0.4.9 Category: tool
ascodev 21 July 2013; 06:54

ASCO is a SPICE circuit optimizer used to design high performance analog low-power low-voltage circuits for mobile communications. The key features of the ASCO tool are:

  • Simulator independent: currently out-of-the-box support for Eldo (TM), HSPICE (R), LTSpice (TM), Spectre (R), Qucs and ngspice exist. More are to be included in future releases.
  • Number of variables: there is, in theory, no limit to the number of circuit variables that can be optimized, except those constraints imposed by the available computer memory and/or the time required to generate a functional circuit. It is currently hardcoded in the C code.
  • PVT corners: by using the simulator functionality, the possibility to test various design corners and Monte Carlo analysis is only limited to the simulator capability and by the time it takes to finish the optimization.
  • Efficiency: the optimization algorithm features a global optimization using differential evolution. It has been used on a variety of applications and is know to produce good results in an acceptable time.
  • Within the supported SPICE simulators, arbitrary netlist can be optimized on different conditions without having to recompile the code.
  • File format: all outputted data and log information is stored in plain text format. This guarantees that they will be always readable in the future. In addition, it makes possible to use other existing tools to post-process the optimization results.


  • Initial support for ngspice simulator.
  • Corrected memory leak in parallel mode. Minor bug fixes in 'log' and 'postp' tools.

  License: GPL homepage download

openMSP430 xxx Category: design
Olivier Girard 7 February 2013; 16:46

The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430 microcontroller family and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.

The core comes with some peripherals (16x16 Hardware Multiplier, Watchdog, GPIO, TimerA, generic templates) and most notably with a two-wire Serial Debug Interface supporting the MSPGCC GNU Debugger (GDB) for in-system software debugging.

While being fully FPGA friendly, this design is also particularly suited for ASIC implementations (typically mixed signal ICs with strong area and low-power requirements). In a nutshell, the openMSP430 brings with it:

  • Low area (8k-Gates), without hidden extra infrastructure overhead (memory backbone, IRQ controller and watchdog timer are already included).
  • Excellent code density.
  • Good performance.
  • Built-in power and clock managment options.
  • Multiple time Silicon Proven.
  License: BSD homepage download

YASEP 2009 Category: design
Yann Guidon 21 October 2012; 08:10
YASEP (Yet Another Small Embedded Processor) is a configurable microprocessor core (16 or 32 bits, instruction set and other features...) written in VHDL and designed with HTML+JavaScript. The website is completely downloadable and contains tightly integrated resources: documentation, assembler, disassembler, configurator, self-tests. The website is more than an IDE because the same tools are used for designing/defining the core AND using it ! And the learning curve is very smooth since there is NO tool or software to get, install and learn.
  License: Other homepage download

OpenTech Category: announcement
Khatib 21 October 2012; 08:02

OpenTech is the first and largest world wide package of free open source hardware designs, EDA software and Books for electronics designs. Since 2000 we have sold OpenTech packages to Students, Professors, Engineers, Startup and even large corporations. In OpenTech package you will find many things that you can not imagine they even exist as open source. Most of the OpenCollector Tools and Designs are available in OpenTech and even more. You will find CPUs , Ethernet, USB and other 300 designs. VHDL, Verilog, Schematic, IC and board layout and many many other software programs more than 300 programs. In short you will find lot of information that helps you in designing your system or testing it.

The package is composed of 5 DVDs that costs only 90 Euros. Use free open source tools and designs in OpenTech package and save more than $500,000 and more than 3 months of search and download time.

This release is the 16th release since the start of OpenTech in 2000 and contains

  • More than 16 GB of information distributed
  • More than 380 Electronics related software
  • More than 85 Hardware designs
  • More than 670 Ope Cores
  • More than 15 free books & tutorials

Since 2000 more than 660 shipped CDROMs/Packages all over the world. This package is composed of 5 DVDs (Tools, Designs, Open Cores, and Books) and it features EDAutils,

We offer new service, we can help you in finding free designs or tools by posting your requests to and we will share the information on our Facebook page.


qucsStudio 1.4.2 Category: tool
21 October 2012; 07:17

QucsStudio is mainly a circuit simulator that has evolved out of the project Qucs, but isn't compatible with it. It's meant to be a test project to create a complete development environment for electrical engineers (graphical user interface with circuit simulator, PCB layouting, numerical data processing etc).

Though based on QT and other platform-independent systems the current version runs only on Windows or under Wine on Linux.

  License: GPL homepage

OsmoSDR Category: design
gs 6 July 2012; 04:29

OsmoSDR is a 100% Free Software based small form-factor inexpensive SDR (Software Defined Radio) project. It consists of a USB-attached Hardware, associated Firmware as well as GrOsmoSDR gnuradio integration on the PC.

Hardware schematics and firmware source code are kept in a git repository.

  License: GPL homepage download

VHDocL 0.2.3 (Dec 2011) Category: tool
nuess0r, because he likes VHDocL 20 June 2012; 03:20
VHDocL - a VHDL documentation utility

In the software world, documentation tools abound. Doxygen, javadoc, kdoc and others allow to extract specially formatted comments from source code and generate a set of interlinked HTML pages giving the annotated class structure of the program.

VHDocL serves to document a hardware design at the structural level. Signals, formulas, function bodies and other functional components of the source code are ignored. Entities and architectures, function declarations, constants, processes, instantiations, generate statements and other constructs relating to the structure of the design are parsed and documented in HTML pages. As with other documentation generators, the code can be annotated with special comments which will be added to the HTML documentation.

The HTML ouput is interlinked extensively: instantiations are linked to the declaration of the component and to the entity to which it is bound. Bindings are determined across libraries if necessary and taking for...use statements into account. VHDocL also supports configurations.

From a presentational point of view, the generated documentation can be customised by a CSS style sheet file provided by the user, and by up to two logos displayed on every page.

VHDocL has been tested on a number of open-source designs and is being used on FPGA designs by me and by colleagues as well as larger ASIC designs. It is considered stable enough to be unleashed on an unsuspecting community of VHDL coders.

Features blurb

  • Documents entities, architectures, configurations and packages and their declarations, processes and instantiations
  • HTML tags and images allowed in descriptions
  • Collective descriptions for groups of ports, generics or constants
  • Corporate identity appearance through optional logos and style file
  • Source code syntax highlighting, customisable by user style file
  • Supports attributes, configurations and multiple libraries
  • Component instantiations resolved, taking into account for...use statements and configurations
  • Partial support for Accelera's Property Specification Language (PSL)
  • Supports versioning information substituted by Subversion version management system

Recent improvements:

  • Syntax highlighting by CSS classes, allowing user customisation
  • The parsing and processing runtime has been greatly reduced in version 0.2
  • Clearer presentation through hierarchical instantiation view and syntax highlighting

  License: GPL homepage download

logpro v1.03 Category: tool
Matt Welland 24 September 2011; 15:00
With logpro you can write command files to rigorously analyze log files. For example you may have a complex simulation with many steps, compilation, simulation, analysis, clean up etc. You want to know in an automated way if the simulation ran. Manually reading the log file(s) once or twice searching for errors, warnings and messages is fine but by the third or forth time you want to automate it. Logpro can help.
  License: GPL homepage download

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