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layout editor 20091228 Category: tool
J. Thies 27 December 2009; 06:48
A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, crossplatform compatible, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), DXF, CIF (Caltech Intermediate Form), Gerber, LEF, DEF, ...

Update
New features: direct load of gzip'ed files, support of compressed blocks in saving OASIS, automatic mapping of layer/datatype possible, SOURCE file format, increase layers to 1024, new setup of used layers (default 128), new mosis example library, photonic devices in the shape library, new distributions (e.g fedora 12), ...

  License: GPL homepage download
Covered 0.7.7 Category: tool
Trevor Williams 25 October 2009; 01:35
Covered is a Verilog code coverage utility that reads in a Verilog design and generated VCD/LXT dumpfile (or runnable in VPI module form) from that design and generates a coverage file that can be merged with other coverage files and/or used to create a coverage report. Covered also contains the coverage report utility that reads in a coverage file to produce human-readable coverage reports viewable in ASCII or GUI form. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state and FSM state transition, and assertion coverage.

Update
Bug fix release.

  License: GPL homepage download
YASEP 2009 Category: design
Yann Guidon 18 October 2009; 02:06
YASEP (Yet Another Small Embedded Processor) is a configurable microprocessor core (16 or 32 bits, instruction set and other features...) written in VHDL and designed with HTML+JavaScript. The website is completely downloadable and contains tightly integrated resources: documentation, assembler, disassembler, configurator, self-tests. The website is more than an IDE because the same tools are used for designing/defining the core AND using it ! And the learning curve is very smooth since there is NO tool or software to get, install and learn.
  License: Other homepage download
The TimingAnalyzer 0.931 Category: tool
30 August 2009; 10:34
A tool for drawing timing diagrams and performing timing analysis. It is written in java and runs on JRE/JDK 1.6.0. Tool supports python scripting.
  License: Other homepage
Mr.Filter 0.1 Category: tool
Alan Somers 23 August 2009; 18:26
An active filter design assistant. Electrical engineers can use it to design and simulate analog active filters.
  License: GPL homepage download
Toped O.94 Category: tool
gs 7 August 2009; 18:58
Toped is an open source cross-platform IC layout editor, based on openGL and wxWidgets. The project defines its own scripting language - TELL, capable not only of configuring the editor properties, but also of coding and facilitating layout generation. All operations are executed as a response to a TELL command. There is no need to type every command - each menu item or shortcut generates one. The main focus is on the speed of the rendering and the details and quality of the layout view. The user is free to use the full power of openGL in terms of colors and fill patterns. Output can be exported to GDSII.

Update

  • New graphic renderer (Requires OpenGL 1.4 support). Rendering speed improved by up to 3 times. Old rendering remains for platforms with limited OpenGL support.
  • Updates of the internal layout database to improve the speed and memory footprint.
  • GDSII rendering updates and optimizations.

  License: GPL homepage download
Qi Hardware Category: community
gs 1 August 2009; 17:35

Qi Hardware is a company started by former OpenMoko employees. It builds copyleft hardware running a stable linux kernel and free software. The company is founded on a belief in open hardware, and produces mass market quality hardware applying free software principles to consumer electronics. The company say:

Only if developers truly know how the device functions can they exploit its maximum potential, only if we maintain and move the kernel upstream can applications make use of the newest technology, and only if we listen to the community and work together with our customers can we redefine freedom.
  homepage
BYU Edif Tools 0.5.1 Category: tool
gs 12 July 2009; 06:36

BYU EDIF Tools is an API for creating, modifying, or analyzing EDIF netlists within the Java programming language. The current release includes the following tools:

  • Java parser to parse pre-generated EDIF netlists
  • JHDL generator for circuits represented in the EDIF data structure
  • View EDIF circuit structure
  • Simulate circuits (EDIF netlists based on Xilinx primitives)
  • Integrate custom JHDL GUI tools
  • EDIF merging routines for merging multiple-file EDIF circuits
  • Primitive library for Xilinx FPGAs
  • Automated TMR (Triple Modular Redundancy) application
  License: GPL homepage download
gerbv 2.3 Category: tool
Stefan Petersen 12 July 2009; 06:28

Gerbv is the open source RS-274X (a.k.a. Gerber) and NC drill (a.k.a. Excellon) file viewer. Gerbv is a cross platform tool which should work on all modern unix-like operating systems. In addition, windows is supported by way of a binary installer.

Update
Many bug-fixes and improvements

  License: GPL homepage download
Fedora Electronic Laboratory Category: announcement
gs 25 June 2009; 03:56

Fedora have approved the creation of a new 'Electronic Laboratory'. The aim is to provide all the tools needed for an environment for designing and simulating ASIC design and embedded design. The opensource EDA solutions are composed to satify high-end mixed-signal hardware design flows from design specification to final project handoff.

The organizer, Chitlesh Goorah, has a blog likely to have the latest news.

Update

This release comprises Perl modules to facilitate both design, HDL code generation and brings additional support for Engineering Change Order (ECO). After post chip fabrication, evaluation boards of those chips can also be designed.

Existing RPM packages were updated to improve design experience in terms of development time and debugging. The key highlights of the major development items put the quality barrier higher than the previous releases:

  • Perl modules to extend vhdl and verilog support. These Perl modules together with gtkwave improves chip testing support.
  • Perl parsers for VHDL, Verilog and SystemC.
  • Introduced collaborative development solutions.
  • Introduction of Verilog-AMS modeling into ngspice.
  • Improved VHDL debugging support with gcov.
  • Improved support for re-usable HDL packages as IP core.
  • Improved PLI support on both iverilog and ghdl
  • Introduction of C-based methodologies for HDL testbenches and models.
  • Improved co-simulation based hardware design.
  • Introduction of design tools for DSP design flow.

  homepage
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